Strained silicon-on-insulator structures for semiconductor devices combine the benefits of two advanced approaches to performance enhancement: silicon-on-insulator (SOI) technology and strained silicon (Si) technology. The strained silicon-on-insulator configuration offers various advantages associated with the insulating substrate, such as reduced parasitic capacitances and improved isolation. Strained Si provides improved carrier mobilities. Devices such as strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) combine enhanced carrier mobilities with the advantages of insulating substrates.
Strained-silicon-on-insulator substrates are typically fabricated as follows. First, a relaxed silicon-germanium (SiGe) layer is formed on an insulator by one of several techniques such as separation by implantation of oxygen (SIMOX), wafer bonding and etch back; wafer bonding and hydrogen exfoliation layer transfer; or recrystallization of amorphous material. Then, a strained Si layer is epitaxially grown to form a strained-silicon-on-insulator structure, with strained Si disposed over SiGe. The relaxed-SiGe-on-insulator layer serves as the template for inducing strain in the Si layer. This induced strain is typically greater than 10−3.
This structure has limitations. It is not conducive to the production of fully-depleted strained-semiconductor-on-insulator devices in which the layer over the insulating material must be thin enough [<300 angstroms (Å)] to allow for full depletion of the layer during device operation. Fully depleted transistors may be the favored version of SOI for MOSFET technologies beyond the 90 nm technology node. The relaxed SiGe layer adds to the total thickness of this layer and thus makes it difficult to achieve the thicknesses required for fully depleted silicon-on-insulator device fabrication. The relaxed SiGe layer is not required if a strained Si layer can be produced directly on the insulating material. Thus, there is a need for a method to produce strained silicon—or other semiconductor—layers directly on insulating substrates.
Double-Gate MOSFETs
Double gate MOSFETs have the potential for superior performance in comparison to standard single-gate bulk or single-gate SOI MOSFET devices. This is due to the fact that two gates (one above and one below the channel) allow much greater control of channel charge then a single gate. This configuration has the potential to translate to higher drive current and lower stand-by leakage current.
FinFETs
Fin-field-effect transistors (finFETs), like double-gate MOSFETs, typically have two gates (one on either side of the channel, where the channel is here oriented vertically) allowing much greater control of channel charge than in a single gate device. This configuration also has the potential to translate to higher drive current and lower stand-by leakage current. Devices related to the finFET, such as the wrap-around gate FET (gate on both sides of as well as above the channel) allow even more channel charge control and hence even more potential for improved drive current and leakage current performance.
Bipolar-CMOS
The bipolar-CMOS (BiCMOS) process is a combination of both the bipolar transistor and MOSFET/CMOS processes. Individually, the CMOS process allows low power dissipation, high packing density and the ability to integrate complexity with high-speed yields. A major contribution to power dissipation in CMOS circuits originates from driving the load capacitance that is usually the gate of sequentially linked logic cells. The size of these gates may be kept sufficiently small, but when driving higher loads (such as input/output buffers or data buses) the load or capacitance of such devices is substantially larger and therefore requires greater gate width (hence area) of transistor, which inevitably drives down the switching speed of the MOSFET.
The bipolar transistor has significant advantages in terms of the drive current per unit active area and reduced noise signal. Additionally, the switching speed is enhanced due to the effectively exponential output current swing with respect to input signal. This means that the transconductance of a bipolar transistor is significantly higher than that of a MOS transistor when the same current is passed. Higher transconductance enables the charging process to take place approximately ten times more quickly in emitter coupled logic circuits, or high fan out/load capacitance.
Pure bipolar technology has not replaced the high packing density microprocessor CMOS process for a number of reasons, including issues of yield and the increased area required for device isolation. However, integration of bipolar and CMOS may provide the best aspects of the composite devices.
The advantages of BiCMOS process may be summarized as follows:                1. Improved speed performance of highly integrated functionality of CMOS technology;        2. Lower power dissipation than bipolar technology;        3. Lower sensitivity to fan out and capacitive load;        4. Increased flexibility of input/output interface;        5. Reduced clock skew;        6. Improved internal gate delay; and        7. Reduced need for aggressive scaling because a 1–2 μm BiCMOS process offers circuit speed equivalent to that of sub-micron CMOS.        